Base · 8453

Solid-State Thermal
Oscillation Control

Toroidal Peltier Architecture · Thermodynamic Computing
v1.0 · Design Base Mainnet Physics: Proven Prototype: Q4 2026
Chip primitive
Toroidal Ring
N Peltier junctions around a closed loop, driven by phase-shifted currents. A coherent thermal wave propagates as the computational medium.
Substrate
Bi₂Te₃ / Si
Topological-insulator legs on silicon back-end. ZT* ≈ 1.42 at wafer scale — geometric gain, no new materials.
Φ
ISA
NWO-ASM · stoc
Twelve native instructions. Free-energy optimiser routes any process-matrix program to a physical ring.
Financing
Base 8453
Single MetaStateSplitter shared with NWO-ASI & NWO-Metaverse. One deposit funds three products.
What this is
A chip that computes with heat, not against it.
Silicon logic has hit a thermal wall. Roughly forty per cent of a modern data-centre's grid input is spent moving heat away from switching transistors. STOC turns that inversion on its head: instead of fighting heat with plumbing, use heat as the computational medium. Peltier junctions arranged around a closed ring, driven by phase-shifted currents, support a coherent traveling thermal wave. Temperature becomes the state variable. The ring clocks itself.
This is not a Second-Law violation. STOC sits inside the Second Law — it maximises the coefficient of performance (COP) of a topologically closed thermodynamic cycle. The gain is geometric, not miraculous: a ring has no ends, so accumulated heat re-enters the useful loop instead of being dumped as waste.
Why now. Osaka QIQB brought a real ion-trap online through OQTOPUS Cloud in late 2025. Bi₂Te₃ nanowire ZT>2 was measured in 2008. NWO-ASM has three live QPU backends already. STOC is the fifth substrate — the one you can build on a tabletop.
01 · Flowchart
Physics of the STOC device
Horizontal information flow — inputs on the left, the toroidal ring in the middle, outputs on the right. The ring is 3D and can be rotated and zoomed. Hover the nodes for a quick summary; click for the underlying equations.
Input · A
Phase-shifted current
Iᵢ(t) = I₀·cos(2πi/N − ωt) — the drive waveform.
Input · B
Axial B-field
Permalloy core supplies B for Nernst-gated direction.
Input · C
Ambient bath
T_C reference at inner header, T_H at outer.
Input · D
Process matrix
PMX IR from NWO-ASM compiler.
mode m = 1
ω/2π ≈ 398 Hz
N segs 24 · tabletop
Output · α
T(θ,t)
Traveling wave amplitude & phase — read via IR array.
Output · β
COP
Coefficient of performance at m = 1 optimum.
Output · γ
Signed receipt
Ed25519 on-die + on-chain proof-of-inference.
Output · δ
USDC settlement
Base 8453 · shared splitter · atomic 35/35/30 + 15%.
Static functional nodes
The eight functions the ring performs

Peltier junction

The elemental unit: current I through an n-p junction pumps Π·I heat across the interface, with Π = S·T (Peltier coefficient).

PROVEN

Seebeck read-out

A ∇T gradient across the junction generates a voltage V = −S·∇T. Cross-terminals every 2π/N radians read T(θ).

PROVEN

Thomson bulk term

Current through a temperature gradient adds q_Th = −μ_Th·J·∇T where μ_Th = T·dS/dT. Small correction at 300 K.

PROVEN

Nernst gating

Axial B-field lifts spin degeneracy near the Bi₂Te₃ Dirac cone, gating wave direction. Clockwise for B·ẑ > 0.

PROVEN

Ring dispersion

ω(m) = m·Π·I₀ / (ρ·c_p·A·R). Linear in azimuthal number m — coherent multi-mode superposition allowed.

DESIGN

Maximum-COP mode

∂COP/∂m = 0 → m = 1 wins. A single traveling wave outperforms uniform drive and higher harmonics.

DESIGN

Effective ZT*

ZT* = ZT_bulk·(1+η_ring). η_ring ≈ 0.14 tabletop, 0.42 wafer scale. Geometric gain — no new material.

DESIGN

Thermal memory

Relaxation time τ = ρ·c_p·R²/κ. Bit encoded as wave-phase; refresh needed every τ. Off-chip PCM for persistence.

DESIGN
Scale comparison
Tabletop → industrial
ScaleN segsRing Rω / 2πη_ringZT*Dies / waferStatus
Tabletop2450 mm≈ 400 Hz0.141.141 unitPLANNED Q4 2026
Hex tile24015 mm≈ 12 kHz0.221.2250-100/moDESIGN 2027
Wafer demo1,0245 mm≈ 1.6 MHz0.321.32200DESIGN 2027
3D-IC pilot128 × 81 mm≈ 25 MHz0.421.425,000ROADMAP 2028
Industrial10⁸ / die5 μm≈ 400 MHz0.421.4210⁶+ /yrROADMAP 2029+
02 · Architecture
Full system capability
A rainbow-gradient flowchart of the STOC stack — from raw materials at the bottom to compiled programs at the top. The gradient itself is a physical metaphor: information does not "forget" as it flows across the ring, because the closed loop keeps it entropic in a controlled way. Maxwell's demon sorts phase, not molecules.
The Maxwell's demon connection. In the ring, phase coherence replaces Landauer erasure as the dominant cost. Because the ring is topologically closed (S¹×S¹), a bit encoded as the phase of a traveling wave doesn't need to be erased to be over-written — it simply propagates around and is refreshed by the drive. The Landauer bound kT ln 2 still applies per erased bit, but STOC's steady-state bit-turnover per operation is dominated by ring dissipation, not by erasure, and can be made arbitrarily small by tightening m and lengthening τ_relax. Environmental positive effect: fewer erasures per computation → less waste heat per bit → smaller cooling load per FLOP.
Layer 09
Application
NWO-ASI · NWO-Metaverse · third-party programs written against NWO-ASM.
Layer 08
Runtime
Free-energy optimiser routes PMX IR to best-fit substrate at call time.
Layer 07
Compiler
.nwo → PMX IR → ring drive schedule. LLVM 17 for classical fall-back.
Layer 06
Substrate
stoc · CPU · GPU · qpu.ibm · qpu.origin · qpu.osaka · ecg_hive.
Layer 05
Verification
Ed25519 on-die + PoI re-verification + Base anchor. No claim without a signed receipt.
Layer 04
Ring stack
8 planar rings on 22 nm CMOS. TSVs couple layers → S¹×S¹ topology.
Layer 03
Peltier legs
n-Bi₂Te₂.₇Se₀.₃ · p-Bi₀.₅Sb₁.₅Te₃ · 40 nm × 40 nm × 900 nm each.
Layer 02
Sensors
128×128 IR microbolometer or InGaAs plane bonded on top. NETD 15 mK.
Layer 01
Materials
Si substrate · Cu headers · SiN passivation · permalloy core (prototype).
Production plan
Three fabs, two paths

Path A · MEMS pilot

6-inch wafers, 1 μm feature size, MBE for Bi₂Te₃ legs. Cycle 6-8 weeks. €25 k/wafer. Suitable for the 10-ring hex tile and small-batch delivery.

DESIGN · Q2 2027

Path B · Tier-1 3D-IC

22 nm CMOS + Bi₂Te₃ back-end + 8-layer stacking. Cycle 14-18 weeks. €90 k/wafer. Yield-limited by TSV planarity, currently ≈ 40 %.

ROADMAP · 2028

Materials · sourcing

Primary Bi₂Te₃ from Kurt J. Lesker or Sigma-Aldrich; permalloy from Magnetics. Half-Heusler ZrNiSn Te-free hedge for the outer ring. Recycled Te from EOL CdTe modules.

SOURCES PROVEN
Interdisciplinary tech stack
DisciplineContributionLayer
Solid-state physicsOnsager coefficients, Peltier/Seebeck/Thomson03
TopologyS¹×S¹ (torus) via stacked planar rings04
Materials scienceBi₂Te₃ epitaxy on Si (111) with Bi₂Se₃ buffer03
Semiconductor fab22 nm CMOS + back-end Bi₂Te₃ integration03-04
Electrical engineering128-ch PWM driver plane, current-sense H-bridges04
Signal processingDFT of T(θ) → complex spectrum05
Compiler designPMX IR → ring schedule lowering (NWO-ASM)07
CryptographyEd25519 on-die + Base 8453 anchor05
Distributed systemsSubstrate contract + free-energy routing08
EconomicsMetaStateSplitter · 35/35/30 + 15% affiliate09
03 · Metrics
Thermal state ontology & efficiency envelope
A closed thermodynamic system has a specific ontology: every state maps to a Fourier decomposition of T(θ) around the ring. Below are the four canonical metrics — entropy per cycle, power in vs out, COP envelope, and data-transfer efficiency — that STOC exposes to the runtime.
Entropy / cycle
≈ 0
Reversible limit · Carnot bound
Landauer / bit
1 kT ln 2
Only at erasure — bypassed in ring
COP @ m = 1
3.4 – 5.8
Depends on ΔT window
Efficiency vs CPU
6.7×
FLOP/W · projected wafer scale

Entropy production per drive cycle

ΔS_univ = Q_H/T_H − Q_C/T_C · vs mode m

Power in vs power out

W_in vs Q_C — the pump characteristic

Coefficient of performance envelope

COP = T_C / (T_H − T_C) · f(m,ω)

Load-vs-in/out efficiency

Load kernel · dispatch cost across substrates
Ontological structure of thermal states
Each state is a point in complex Fourier space
The ring's temperature field T(θ,t) decomposes uniquely into complex Fourier harmonics T̂(m,t) = ⟨T(θ)·exp(−imθ)⟩. For N = 128 segments the eight lowest harmonics (m = 0…7) carry the useful information — beyond that, the amplitudes drop below the IR NETD. Each harmonic is a complex number, so single-ring state space is 16-real-dimensional; 8-layer 3D-IC gives 128-D; a 10⁶-ring wafer gives 1.28×10⁸-D — comparable to a modern GPU's L2 but continuous and thermal.
Mode mMeaningAmplitude (typ.)Role
0Uniform DC offset< 20 mKGlobal bath drift — filtered out
1Single traveling wave0.5 – 2.5 KPrimary state carrier · clock
2Standing double lobe0.1 – 0.6 KEven-parity data lane
3Triple lobe0.05 – 0.3 KOdd-parity data lane
4…7Higher harmonics0.01 – 0.1 KEncrypted / paranoid modes
05 · RISC-V STOC
Seven RISC-V + STOC configurations
Paper II enumerates the seven distinct ways to combine the open-standard RISC-V ISA with the STOC toroidal Peltier ring. Each trades silicon area, thermal-oscillation fraction, and programming-model complexity differently. The vertical map below flows from the CPU-in-orbit at the top, out through 7 rainbow motherboard traces, down through 7 strings of technical detail, and converges into a prism at the bottom — from which the thermodynamic equations of each configuration emerge as spectral output.
Config A
RV core + STOC coprocessor
Custom-0 opcodes. Ring bonded post-fab. Simplest path. Silicon Q2 2027.
Config B
Peltier thermal L2 cache
SRAM L2 replaced with ring array. 10× lower dynamic P; +30% read latency.
Config C
STOC integer ALU
Ring-superposition adder. Phase-convolution multiplier. Zstoc-alu extension.
RISC-V
Config D
STOC persistent memory
τ-relaxation as non-volatile. Same telluride family as PCM. ∞ endurance.
Config E
STOC ring interconnect
Multi-core cache-coherence via phase pulses. Interconnect 10% → 1% of die.
Config G
Distributed RV+STOC swarm
Many small nodes coordinated by NWO-ASM free-energy routing.
Config F · center
Fully thermal RISC-V
Every pipeline stage = ring. Hz–MHz clock, μW power. Cryogenic + deep-space + rad-hard.
Configuration deep dive · click any node
Seven strings · seven pillars of detail
Each vertical string carries the technical anatomy of one configuration — physics, energetics, output, power, memory, economics, thermodynamics. Hover a node for a summary; click for the full schema, math, and output estimates.
The prism · convergence
Seven inputs. One spectrum.
The seven rainbow strings converge into a triangular prism. What emerges as the spectral output are the thermodynamic equations that govern each configuration — the underlying invariant physics that all seven share, refracted into their configuration-specific forms.
ΔSuniv ≥ 0 Π = S·T ω(m) = m·Π·I₀ / (ρ·cp·A·R) T(θ,t) = T̄ + δT·cos(mθ − ωt) COP = TC / (TH − TC) · f(m,ω) ZT* = ZTbulk·(1 + ηring) F ≥ kBT ln 2 (Landauer)
Paper II · full analysis
Read the full research paper
Detailed math, per-config economics, market analysis ($4B SAM by 2030), supply-chain risk analysis (RISC-V fab + Bi₂Te₃ Te dominance), and precise NWO-ASM build requirements per configuration. Full physics, mathematical framework, and adoption path in §Paper & Podcast.
06 · STOC ΔT Harvest
Turn every ΔT into compute
The world already runs a giant, always-on temperature-gradient infrastructure. Refrigerators, air conditioners, chilled-water data centres, cold-chain trucks, LNG plants, EV battery loops, and semiconductor-fab cooling all maintain a ΔT round the clock. Today, that ΔT is pure overhead. STOC harvests it. Each cooled system simultaneously performs its native cooling function and becomes an edge thermodynamic-computing node under the NWO-ASM stoc substrate contract.
Cold side · data flow
Hot side · energy flow
B/W shimmer · data · cold-side ·   ·   rainbow shimmer · energy · hot-side
Ten physics nodes ring the central snowflake — the traveling thermal wave that STOC establishes on top of an existing cooling cycle. Cold-side nodes (left) show white/black data-flow shimmer; hot-side nodes (right) show rainbow energy-flow shimmer. Hover any node for a summary; click for the full physics, math, energy input/output, and scale-up details from tabletop to industrial.
Three canonical variants
From household plug-in to industrial wafer-stack
The framework partitions into three price/integration tiers. Each targets a different customer, uses different STOC configurations from Paper II, and requires different NWO-ASM build effort.
Variant I
Household · Cryo-Plug
€ 150-250 retail

Wall-outlet passthrough with embedded 24-segment STOC ring. Couples to fridge's existing ΔT via flexible copper heat pipes. No refrigerant handling, no compressor modification, any UL/CE-listed fridge is a target.

· Config A coprocessor
· SiFive E31 · Wi-Fi/Zigbee
· Anomaly.score kernels
· Smart-home routing
· Predictive maintenance
· Ships Q3 2027 Kickstarter
Variant II
Commercial · Native integration
€ 600-900 retail

Native 22 nm RV64GC SoC with L2 SRAM cache replaced by Peltier ring array. Fridge's cold interior acts as ideal cold-side sink. Compressor duty cycle phase-locked to ring drive at ω_lock = 2·ω_compressor / N.

· Config B thermal L2 cache
· Config D persistent memory
· Inventory tracking (IR + load-cell)
· Cold-chain anomaly scoring
· Customer kiosk inference
· Grocery pilot Q4 2027
Variant III
Industrial · Wafer-stack
€ 2,500 - 12,500

Wafer-scale 8-layer 3D-IC Peltier stack. Config-E ring interconnect for rack-scale coherence. For cryogenic applications (LNG, H₂), Config-F fully thermal RISC-V core operating at μW power in the deep-cold environment.

· Config E ring interconnect
· Config F fully thermal (cryo)
· Autonomous cold-chain logistics
· Zero-power secure data vault
· LNG / H₂ / air-separation
· Roll-out 2028-2029+
Ten cooling verticals
Aggregate TAM · $ 875 B by 2030
The STOC-cooling framework applies wherever a ΔT is maintained on purpose. Ten specific verticals from HVAC to LNG cryogenic, with total addressable market by 2030 in USD billions.
Economics
Per-unit BOM & margin across verticals
Aggregate 2030 revenue
€ 480 M
Gross · summed across verticals
Blended gross margin
84 %
Weighted by volume
Marketplace fees
2 %
On settled tx · Base 8453
5-yr IRR
~ 58 %
Deep-tech benchmark
Variant / ProductBOM €MSRP €GM %Vol 2027Vol 2030
I · Cryo-Plug (household retrofit)72199645,0001.2 M
II · Commercial fridge (native)956998650055 k
II · Commercial display case1401,2998930028 k
III · Industrial reefer4803,49986504 k
III · LNG cryogenic node1,20012,50090150
HVAC retrofit board655498824 k
Data-centre STOC card3202,499875 k
EV BMS add-on2819986320 k
Per-unit economics across variants and verticals. BOM in 2026 EUR; MSRP includes NWO-ASM software subscription for first 3 years.
Supply-chain risk analysis
Fab exposure · Te dominance · OEM channel

Fabrication

Variant I is fully commodity: SiFive/Andes MCUs, Marlow Peltier modules, Toshiba H-bridges. No cutting-edge dependencies. Variants II/III inherit Paper II supply chain: TSMC/Samsung for advanced-node CMOS, SMIC/HH-Grace as sovereign hedges.

MITIGATED

Tellurium (Bi₂Te₃)

60% of refined Te is Chinese. Three hedges: (a) half-Heusler ZrNiSn Te-free substitute at 30% ZT penalty for Configs C/E/F; (b) recycled Te from EOL CdTe photovoltaics at 30% below spot; (c) NWO-ASM free-energy optimiser reroutes to CPU/GPU/QPU if STOC becomes materially constrained.

HEDGED

Appliance-OEM channel

Variant II depends on Whirlpool / Bosch / Haier / Samsung / LG / Electrolux distribution. 24-36 month product cycles, conservative silicon bets. Mitigation: license the reference design at low up-front cost; seed Variant I retrofit market first so ecosystem exists before OEMs commit.

CHANNEL RISK
Risk severity · high-rise view
Every risk from the Paper III register, ranked by probability × impact. Rainbow shimmer flows top-to-bottom on each bar showing continuous ecosystem hedging.
UL/CE certLOW
PLL lock lossLOW
Ring driftLOW
Water contam.MED
Te supplyMED
OEM channelMED
RegulatoryMED
Cold-chain compl.MED
Config F delayHIGH
EV OEM accessHIGH
LOWMEDIUMHIGH
Path to global thermal compute
Six-stage roadmap
From Q4 2026 Cryo-Plug prototype to 2029+ full cryogenic + industrial fab-out. Every stage aligns with an NWO-ASM release, a market-partner engagement, and a compute vertical unlock.
Q4 2026
Cryo-Plug prototype
Bench build against Whirlpool reference. First anomaly.score kernel via Config A opcodes.
PLANNED
Q2 2027
Cryo-Plug Kickstarter
500-unit run at €199. Open-source software; opt-in compute marketplace.
DESIGN
Q4 2027
Variant II grocery pilot
10-store regional chain. Native Peltier-L2 silicon in refrigerated display cases. Target ROI <24 months.
DESIGN
Q2 2028
Data-centre pilot
Tier-3 colocation partner. STOC rings in chilled-water manifolds. Edge compute as tenant SKU.
DESIGN
Q4 2028
HVAC + cold-chain
Rooftop-unit HVAC OEM + reefer container manufacturer. Two parallel silicon shuttles.
DESIGN
2029+
Cryogenic + industrial fab-out
LNG, H₂, air separation. Semi-fab process cooling. Pharma cold storage. Reference deployments.
ROADMAP
Paper III · full analysis
Read Paper III
Complete physics of computing atop a maintained cooling cycle, entropy accounting, 14-vertical integration matrix, Cryo-Plug BOM spec, industrial cold-chain node BOM, and risk register. Available in §Paper & Podcast.
04 · NWO-ASM Integration
STOC is substrate #05
NWO-ASM (Neural Wave Operator Assembly) is the MIT-licensed universal compute assembly language published at cpater-nwo-asm.static.hf.space. Programs written against the process-matrix IR are routed to whatever substrate best fits: CPU, GPU, three QPU backends (IBM · Origin · Osaka), the ECG hive, and — with this project — stoc, the toroidal Peltier ring. Same substrate contract, same free-energy optimiser, same Base 8453 splitter.

Substrate contract

Every NWO-ASM substrate implements lift · dispatch · read · verify. STOC's implementation compiles PMX → ring drive schedule, dispatches via USB-C or PCIe, reads via IR-array DFT, and signs with the on-die Ed25519 key.

DESIGN v0.1

Portability

The stoc instruction set does not reference ring topology at the ISA level — it's a general thermodynamic-computing substrate. Other thermal-oscillation chips (linear arrays, spiral, spin-torque nano-oscillators) can implement the same contract and be routed identically.

DESIGN
The twelve native instructions
; ── STOC v0.1 INSTRUCTION SET ─────────────────────────────
stoc.init      ring    N=128  R=5mm  layers=8
stoc.load      pmx.reg process_matrix
stoc.set.mode  m=1                     ; azimuthal wave number
stoc.set.freq  omega=2.5e3             ; rad/s
stoc.dir       cw | ccw                ; Nernst gate
stoc.heat.push segment=k  amount=q     ; single-junction pulse
stoc.heat.pull segment=k  amount=q     ; symmetric cool pulse
stoc.oscillate cycles=n                ; run n periods
stoc.read.T    theta -> T_out.reg      ; T(theta) via IR plane
stoc.read.dft  N_harm -> spec.reg      ; Fourier amplitudes
stoc.settle    tau                     ; wait for equilibrium
stoc.dispatch  poi.sig -> receipt      ; sign and settle
Worked example — anomaly.score
The most common MetaState substrate call is anomaly.score(v). On STOC it compiles to:
; anomaly.score(v) on the ring — canonical NWO-ASM path
  use stoc as target
  let W = pmx.lift( v )                ; encode as process matrix
  stoc.init ring N=128 R=5mm layers=8
  stoc.load  pmx.reg W
  stoc.set.mode  m=1
  stoc.set.freq  omega=2.5e3
  stoc.dir cw
  stoc.oscillate cycles=32
  stoc.read.dft  8 -> spec
  let score = free_energy_bound( spec )
  stoc.dispatch poi -> anchor(base)    ; USDC settlement, splitter
  return (score, poi.sig)
Runtime binding. The NWO-ASM runtime picks up an STOC endpoint automatically if STOC_ENDPOINT is set in the environment. The tabletop prototype will expose the endpoint over a local USB-C bridge; the wafer-scale device via PCIe Gen4.
nwo-asm.toml stanza
[substrate.stoc]
status         = "DESIGN"           # flips to LIVE after Q4 2026
endpoint       = "http://stoc.local:7412/v1"
authentication = "bearer"            # api_key from MetaState registration
settlement     = "base:8453"         # same splitter as ASI & Metaverse
affiliate      = true                 # 15% via same splitter
capabilities   = [
  "stoc.init", "stoc.load", "stoc.set.mode", "stoc.set.freq",
  "stoc.dir", "stoc.heat.push", "stoc.heat.pull", "stoc.oscillate",
  "stoc.read.T", "stoc.read.dft", "stoc.settle", "stoc.dispatch"
]
07 · Research & DIY
Build your own ring
The tabletop prototype is deliberately DIY-friendly. Everything except the ring assembly is commercial off-the-shelf; a competent electronics hobbyist with access to a soldering iron, a 3D printer, and a Digilent FPGA board can reproduce the ring in a weekend. Total parts cost: € 1,451. Lead time: ~4 weeks for BOM.
Bill of materials · tabletop
ItemPartQty€ ea€ line
Peltier moduleMarlow RC12-8 · 8×8 mm2438912
Permalloy toroidMagnetics 78928 · Ni-Fe 80/2016868
FPGA dev boardDigilent Cmod A7-35T · Artix-71115115
H-bridge driverToshiba TB6612 × 1212336
IR sensor arrayMelexis MLX90621 × 2 · 16-ch258116
12 V PSU · gatedMean Well GST60A12 · 60 W14242
USB-C bridgeFTDI FT2232HL12222
Aluminium heatsinkCustom · radial fins14545
Thermal grease + miscArctic MX-6 + fasteners13535
Enclosure3D-printed PC-FR16060
TOTAL€ 1,451
Six-month engineering plan

Month 1 · Procurement

BOM ordered · mechanical CAD · 3D-printed enclosure iteration · Verilog PWM engine written & simulated in Icarus.

Month 2 · Assembly

Ring assembly + thermal grease cure · heatsink brazing · power-electronics bring-up on the bench with resistive dummy loads.

Month 3 · First light

Single-segment characterisation · thermal impulse response · IR array calibration against Pt100 reference at three temperatures.

Month 4 · Full-ring drive

m = 0 (uniform) and m = 1 (traveling) modes captured · ω-sweep to extract the dispersion relation ω(m) empirically.

Month 5 · NWO-ASM binding

Register endpoint on metastate-quantum as a fifth backend · publish v0.1 of the STOC ISA · CI/CD via GitHub Actions.

Month 6 · Public demo

Run anomaly.score kernel through the ring · settle payment on Base 8453 live · release CAD/Verilog/Rust under MIT on the HF Space.

Cost analysis · scaling
StageYear€/unitVolume/yrYieldStatus
Tabletop prototype20261,4501-5manual · 100%PLANNED
Hex tile · 10 rings202722050-100≈ 60% first passDESIGN
Wafer demo202790200≈ 40%DESIGN
3D-IC pilot2028405,000≈ 60%ROADMAP
Industrial fab-out2029+1210⁶+≈ 80%ROADMAP
DIY code repository. Once the tabletop is characterised, the Verilog for the 24-channel PWM engine, the Rust host stack exposing the four STOC substrate functions, the Python client, the KiCad electrical schematic, and the 3D-printed enclosure STL will land on github.com/RedCiprianPater/stoc-prototype under MIT.
Fabrication process · tabletop
Step-by-step assembly

1 · Toroid preparation

Wind copper spacers around the permalloy core to define the 24 segment slots. Anneal at 850 °C in N₂ for 2 h to relieve stress. Verify μ_r ≥ 8×10³ using a Fluxgate meter before mounting Peltier modules.

STANDARD

2 · Peltier mount

Apply Arctic MX-6 in a 60 μm layer (measured with a wet-film gauge). Torque each module to 0.4 N·m using an Allen key with a torque limiter. Verify with an IR camera that no segment exceeds 5 K above room ambient at rest.

STANDARD

3 · Interconnect wiring

24 twisted pairs (26 AWG PTFE-insulated) from the H-bridge board to the ring. Route through a shielded loom to keep loop area < 4 cm² for EMC compliance. Terminate with polarised Molex Micro-Fit 3.0.

STANDARD

4 · IR array alignment

Mount the two MLX90621 boards at 12° above and below the ring plane so their fields of view together cover the full circumference with 20 % overlap. Calibrate against a Pt100 reference at 20/40/60 °C in a small oven.

DESIGN

5 · FPGA bring-up

Flash the Cmod A7-35T over USB. Verify all 24 PWM channels output 20 kHz square waves at 50 % duty into a scope. Check phase relationships — adjacent channels 15° apart, complete ring covers 360°.

DESIGN

6 · First characterisation

Sweep I₀ from 0 to 1.2 A in 0.05 A steps at ω = 2.5 krad/s. Record IR array frames. Fit T(θ,t) to A·cos(mθ − ωt); extract η_ring from the residual. Target η_ring ≥ 0.10 to declare Month 3 success.

DESIGN
Reference · Verilog PWM engine
The FPGA fabric runs a lightweight 24-channel PWM generator with phase control. Compiled from ~200 lines of Verilog; fits comfortably in an Artix-7 XC7A35T.
// stoc_pwm.v — 24-channel phase-shifted PWM engine · MIT · v0.1
module stoc_pwm #(
    parameter N     = 24,
    parameter PERIOD = 5000    // 20 kHz @ 100 MHz clk
)(
    input  clk,
    input  rst,
    input  [15:0] i0_amp,       // drive amplitude
    input  [15:0] omega,        // scaled angular freq
    input  [3:0]  m_mode,       // azimuthal mode
    output [N-1:0] pwm_out
);
  reg [31:0] phase [0:N-1];
  reg [15:0] duty  [0:N-1];
  reg [15:0] counter;

  integer i;
  always @(posedge clk) begin
    if (rst) begin
      counter <= 0;
      for (i=0; i<N; i=i+1) phase[i] <= i * (32'h1_0000_0000 / N);
    end else begin
      counter <= (counter == PERIOD-1) ? 0 : counter + 1;
      for (i=0; i<N; i=i+1) begin
        phase[i] <= phase[i] + (omega * m_mode);
        duty[i]  <= cos_lut(phase[i][31:22]) * i0_amp >> 12;
      end
    end
  end

  genvar g;
  generate for (g=0; g<N; g=g+1)
    assign pwm_out[g] = (counter < duty[g]) ? 1'b1 : 1'b0;
  endgenerate
endmodule
Reference · Rust host binding
Rust service running on the host computer, exposing the four STOC substrate functions over HTTP for NWO-ASM to pick up:
// stoc_host.rs — MIT · v0.1 · axum + tokio + serialport
use axum::{Router, routing::post, Json};
use serde::{Deserialize, Serialize};

#[derive(Deserialize)]
struct DispatchReq {
    process_matrix: Vec<Vec<f32>>,
    mode: u32,           // m ∈ {0,1,2,…}
    omega: f32,          // rad/s
    dir: "cw" | "ccw",
    cycles: u32,
}

#[derive(Serialize)]
struct DispatchResp {
    harmonics: Vec<(f32, f32)>,   // (Re, Im) per harmonic
    receipt:   String,             // Ed25519 signature
    backend:   String,             // "stoc:tabletop-v1"
}

#[tokio::main]
async fn main() {
    let app = Router::new()
        .route("/v1/dispatch", post(dispatch))
        .route("/v1/read",     post(read_dft))
        .route("/v1/verify",   post(verify));
    axum::Server::bind(&"0.0.0.0:7412".parse().unwrap())
        .serve(app.into_make_service()).await.unwrap();
}
Performance targets · month 6 exit criteria
MetricTargetMethodStatus
η_ring @ m=1≥ 0.10DFT fit of T(θ,t) residualDESIGN
COP @ ΔT = 30 K≥ 4.5Q_C from Pt100 · W_in from current-senseDESIGN
ω-dispersion linearityR² ≥ 0.95ω sweep 0.5 – 5 krad/sDESIGN
End-to-end kernel latency< 200 msanomaly.score · N=8 · via HTTPDESIGN
On-chain settlement< 3 s post-dispatchBase 8453 · one confirmationPROVEN
Risk register. Highest technical risk is Bi₂Te₃ back-end integration yield at wafer scale (mitigation: MEMS-fab pilot before 3D-IC commit). Highest commercial risk is a Tellurium price/supply shock (mitigation: half-Heusler ZrNiSn is a Te-free substitute at ~30% lower ZT, and recycled Te from EOL CdTe photovoltaics enters the market at 30% below primary). Full risk register in Appendix C of the paper.
08 · Paper & Media
The full research paper
The comprehensive theoretical framework, mathematical derivations, chip architecture, NWO-ASM ISA specification, economics, and geopolitical analysis are published as a single two-column academic paper on ResearchGate, with a companion podcast and the raw PDF hosted on this Space.

Read the paper (PDF)

Solid-State Thermal Oscillation Control · v1.0-DESIGN · 11 pages, two-column academic format · 14 sections + 3 appendices · all equations + honest-status table.

ResearchGate

Full preprint with author information, DOI, citation export. Pater 2026. Deposited on the ResearchGate mainline archive.

Open on ResearchGate ↗

Podcast

A companion audio walking through the same material as a conversation. Same theory, physics-first framing, informal delivery.

STOC · Companion Podcast
Ready · click play
Paper structure · TOC
§SectionPages
1Introduction · motivation · Second-Law reality check1
2Thermoelectric transport in a ring1
3The toroidal Peltier ring · modes · ZT*1
4Chip architecture · 9-layer 3D-IC stack1
5NWO-ASM integration · stoc substrate1
6Tabletop prototype specification · BOM1
7Scaling: prototype → industrial1
§SectionPages
8Computational model · thermal states1
9Economics · TAM · SAM · SOM1
10Geopolitics · tellurium supply chain1
11Financing · MetaStateSplitter integration1
12Honest status of every claim1
13Conclusion1
App A/B/CTOML stanza · ISA transcript · Risk register3
Paper II · RISC-V + STOC configurations
RISC-V + STOC — Seven Configurations
Second paper in the STOC series. Enumerates seven distinct ways to combine the open-standard RISC-V ISA with the toroidal Peltier ring, from bonded coprocessor to fully-thermal pipeline. Per-configuration math, economics, market analysis, supply-chain risk, and precise NWO-ASM build requirements.

Read the paper (PDF)

RISC-V + STOC: NWO-ASM Configurations for Thermodynamic-Augmented Open-ISA Computing · v1.0-DESIGN · 10 pages, two-column academic format · 18 sections + 3 appendices · seven configuration flowcharts + honest-status table.

ResearchGate

Full preprint of Paper II with author information, DOI, citation export. Pater 2026. Deposited on the ResearchGate mainline archive.

Open on ResearchGate ↗

Podcast

Companion audio walking through the seven configurations in a conversational format. Same theory, developer-first framing, informal delivery.

RISC-V + STOC · Companion Podcast
Ready · click play
Paper II structure · TOC
§SectionPages
1Introduction · why RISC-V + STOC1
2Background · RISC-V + STOC recap1
3The seven configurations · matrix + summary1
4Config A · RV core + STOC coprocessor1
5Config B · Peltier thermal L2 cache1
6Config C · STOC integer ALU1
7Config D · STOC persistent memory1
8Config E · STOC ring interconnect1
9Config F · Fully thermal RISC-V1
§SectionPages
10Config G · Distributed RV+STOC swarm1
11NWO-ASM · precise build requirements per config1
12Development plan · nine-quarter roadmap1
13Economics · per-die cost + market segmentation1
14Supply-chain risk · RISC-V fab + Te dominance1
15Adoption prospects · 3-phase path1
16Honest status of every claim1
17Conclusion · references1
App A/B/CBoot sequence · opcode encoding · risk register3
Paper III · STOC × Cooling infrastructure
STOC-Cooled Compute — Refrigeration & Industrial Cooling as Compute Nodes
Third paper in the STOC series. Turns every ΔT into compute — refrigerators, HVAC, chilled-water data centres, cold-chain trucks, LNG plants, EV battery loops, semiconductor-fab cooling. Three canonical variants (household Cryo-Plug €150-250, commercial native €600-900, industrial wafer-stack €2,500+) and ten cooling verticals with aggregate TAM $875 B by 2030. Physics of computing atop a maintained cooling cycle, entropy accounting, complete BOMs, supply-chain risk, and adoption path.

Read the paper (PDF)

STOC-Cooled Compute: Refrigeration Systems and Industrial Cooling Infrastructure as Distributed Thermodynamic Computing Nodes · v1.0-DESIGN · 11 pages, two-column academic format · 15 sections + 4 wide appendices · 5 figures.

ResearchGate

Full preprint of Paper III with author information, DOI, citation export. Pater 2026. Deposited on the ResearchGate mainline archive as publication 412123752.

Open on ResearchGate ↗

Podcast · COLDCOMPUTE

Companion audio walking through the STOC-Cooling framework: the three variants, ten verticals, economics, and the path to global thermal compute.

COLDCOMPUTE · STOC × Cooling
Ready · click play
Paper III structure · TOC
§SectionPages
1Introduction · the world runs on ΔT1
2Background · STOC + substrate contract1
3Entropy in a bounded cooling system1
4Three canonical variants (I / II / III)1
5Ten cooling verticals · deep dive2
6Thermal-electrical coupling model1
7NWO-ASM integration per variant1
8Development plan · 6-stage roadmap1
§SectionPages
9Economics · BOM & margin1
10Market analysis · TAM/SAM/SOM1
11Supply-chain risk1
12Adoption prospects · 3-phase1
13Honest status of every claim1
14Conclusion · references1
App A14-vertical integration matrix1
App B/C/DCryo-Plug BOM · Industrial BOM · Risk register3
09 · Finance
Financial scaling projection
Below are the projected revenue and cost trajectories over the next four years. Each row of the trajectory table above (in R&D) maps to a revenue tier here. All figures in EUR at 2026 pricing; assumptions are the same as §9 of the paper. Every projection is labelled DESIGN or ROADMAP — nothing is claimed as shipping until it ships.
TAM · 2030
$200 B
Global thermoelectric cooling · Grand View Research
SAM · compute segment
$5–8 B
Edge AI + quantum control + space-qualified
SOM · steady state
$60 M/yr
3% share of SAM · industrial fab-out
Gross margin · mature
55 %
Wafer scale · 80% yield

Revenue vs cost · 4-year projection

EUR millions · DESIGN estimates

Unit cost trajectory · €/die

Yield-weighted · MEMS pilot → industrial fab

Cumulative units shipped

Tabletop → hex tile → wafer → industrial

Revenue mix by stream

Hardware · licensing · vertical consumption
Splitter mechanics
Every settlement flows through the same rail
ShareWalletRole
Guardian · 35%0x2E964e1c0e3Fa2C0dfD484B2E6D2189dfCF20958Audit + oversight
Savings · 35%0x86adACe73556FD7b386B5E469eEC0878073d6D30R&D reserve
Operations · 30%0x4f125e835bbc9BbB77607C66dE6D0d32339B936cManufacturing runway
Affiliate · +15%referrer address (set at registration)Atomic same-tx payout
Cash flow · four-year projection
From burn-driven to cash-generative
Cash-flow projection at prototype/tabletop, hex-tile, wafer, and industrial-fab-out stages. All figures in EUR thousands. The pool is designed to weather the first two years of negative EBITDA on the assumption that industrial fab-out (2029+) is the value-realisation event, with hex-tile and wafer sales bridging the gap.
Line item · € 000s20262027202820292030
Hardware revenue183202,10010,40036,200
NWO-ASM licensing0151408203,800
Vertical consumption (ASI+Metaverse)0251809502,400
Total revenue183602,42012,17042,400
COGS · materials + fab4857203,60015,300
R&D · engineering3201,1202,4003,6004,800
G&A · overhead753801,0501,6002,100
EBITDA−381−1,225−1,7503,37020,200
Cumulative EBITDA−381−1,606−3,3561420,214
Break-even year
2029
Cumulative EBITDA turns positive
Peak capital need
€ 3.4 M
End of 2028 · before break-even
IRR · 5-year
~ 62 %
Model at industrial ramp
Valuation methodology
Two independent methods bracket the value. (1) Discounted cash flow — WACC = 22 % (early-stage deep-tech), terminal growth 3 %, five-year explicit forecast + terminal value gives an equity valuation of ≈ € 68 M at industrial ramp. (2) Comparables — Peak Nano ($240 M seed, MRAM), pSemi (Murata, $530 M acquisition), and Ambiq Micro (IPO 2024, $600 M cap) as sector benchmarks; median revenue multiple × 2030 projected revenue gives ≈ € 55–90 M. Midpoint € 70 M at industrial ramp.
MethodAssumptionResult (2030)
DCF · explicit 5-yrWACC 22 % · g 3 % · terminal 10× EBITDA€ 68 M
Revenue multiple · compMedian deep-tech chip × 1.6€ 68 M
Peer transaction · compSeed-stage sensor-chip median€ 55–90 M
Midpoint estimate≈ € 70 M equity value at 2030 industrial ramp
Ownership · dilution across the spectrum
The MetaStateSplitter is not an equity contract — depositors do not receive tokenised equity in the traditional sense. What they do receive is a permanent claim on 35 % of net inflows (via the Guardian wallet, which is jointly custodied) plus a 15 % affiliate line from every downstream deposit. This structure holds identically across STOC, NWO-ASI, and NWO-Metaverse because it is one contract.
RoundAmount raisedPurposeTiming
Pre-seed · shared€ 0 – 500 kTabletop prototype + first-light characterisation2026 · NOW
Seed · shared€ 500 k – 2 MMEMS pilot line + hex-tile production2027 H2
Series A · shared€ 2 – 8 MTier-1 3D-IC engagement + pilot line2028 H1
Growth · shared€ 8 – 25 MIndustrial fab-out · yield ramp2029+
Notice. Every projection above is DESIGN or ROADMAP status. Nothing is shipped. Deposits carry full loss-of-principal risk. This is a speculative deep-tech pool, not a certificate of deposit. Read §9-11 of the paper before committing capital.
10 · Invest
One deposit. Three products.
STOC, NWO-ASI, and NWO-Metaverse all settle through the same MetaStateSplitter on Base 8453. When you deposit into the pool, you gain fractional exposure to all three simultaneously. This is not a fund-of-funds — it is a single audited contract that pays out atomically across the spectrum in the same transaction.
Enter the Pool
Base mainnet · one contract · three products
ETH
EQUITY
Rate1 ETH ≈ 1,000 EQUITY (indicative)
Min0.001 ETH
Splitter · 0x33c2…46bc · Base 8453 · checking…
Live pool telemetry

Total raised (all three products)

Raised · ETH
Base mainnet · live
Deposits
Unique wallets
Median ticket
ETH per deposit
Last block
Refresh every 30 s
Pool age
Time since first deposit
Avg ticket
ETH per deposit

Capital raised over time

Live · Base 8453 · updates on refresh

Recent activity

Last twenty transactions to the shared splitter. Refreshes automatically. Click any block to open on BaseScan.
BlockTimeFromAmount (ETH)Tx
Loading recent deposits…
The spectrum · what you're funding
Same contract. Three verticals.
NWO STOC
Physical chip · this Space
Toroidal Peltier ring · tabletop prototype Q4 2026 · wafer scale 2027 · industrial 3D-IC 2029+. Substrate #5 in NWO-ASM. Financed here.
See the ring →
NWO ASI
Casimir-Sonoluminescence · vacuum-field thruster
Autonomous investment pool financing the ASI vacuum-thruster prototype. Same immutable contract on Base — depositing here funds STOC too, and vice-versa.
Open NWO ASI ↗
NWO Metaverse
L6 shared economy · MR/AR
Mixed-reality shared economy with RunPod GPU/CPU dual-pod routing and 4DGS pipeline. Same splitter — one deposit exposes you to all three simultaneously.
Open Metaverse ↗
Why one contract, not three. Fewer contracts means fewer audit surfaces, no incentive to fragment the affiliate graph, and no risk of a "successful" product cannibalising the others. Investors see a single Base mainnet transaction; the smart contract fans out to the four wallets atomically; the affiliate 15% pays out same-tx to the referrer. If any one of STOC/ASI/Metaverse ships and generates revenue, the entire pool benefits.
Contract · immutable · verified
WhatValue
NetworkBase Mainnet · chain id 8453
Splitter (shared)0x33c22FE36557Ad13C838A2Eb465510CF173046bc
Settlement tokenUSDC · 0x8335…2913
Deposit functiondeposit() payable · or approve+payForInference()
Split35% guardian · 35% savings · 30% ops · +15% affiliate (same tx)
ImmutabilityVerified & unowned · no upgrade key