Solid-State Thermal
Oscillation Control
Peltier junction
The elemental unit: current I through an n-p junction pumps Π·I heat across the interface, with Π = S·T (Peltier coefficient).
PROVENSeebeck read-out
A ∇T gradient across the junction generates a voltage V = −S·∇T. Cross-terminals every 2π/N radians read T(θ).
PROVENThomson bulk term
Current through a temperature gradient adds q_Th = −μ_Th·J·∇T where μ_Th = T·dS/dT. Small correction at 300 K.
PROVENNernst gating
Axial B-field lifts spin degeneracy near the Bi₂Te₃ Dirac cone, gating wave direction. Clockwise for B·ẑ > 0.
PROVENRing dispersion
ω(m) = m·Π·I₀ / (ρ·c_p·A·R). Linear in azimuthal number m — coherent multi-mode superposition allowed.
DESIGNMaximum-COP mode
∂COP/∂m = 0 → m = 1 wins. A single traveling wave outperforms uniform drive and higher harmonics.
DESIGNEffective ZT*
ZT* = ZT_bulk·(1+η_ring). η_ring ≈ 0.14 tabletop, 0.42 wafer scale. Geometric gain — no new material.
DESIGNThermal memory
Relaxation time τ = ρ·c_p·R²/κ. Bit encoded as wave-phase; refresh needed every τ. Off-chip PCM for persistence.
DESIGN| Scale | N segs | Ring R | ω / 2π | η_ring | ZT* | Dies / wafer | Status |
|---|---|---|---|---|---|---|---|
| Tabletop | 24 | 50 mm | ≈ 400 Hz | 0.14 | 1.14 | 1 unit | PLANNED Q4 2026 |
| Hex tile | 240 | 15 mm | ≈ 12 kHz | 0.22 | 1.22 | 50-100/mo | DESIGN 2027 |
| Wafer demo | 1,024 | 5 mm | ≈ 1.6 MHz | 0.32 | 1.32 | 200 | DESIGN 2027 |
| 3D-IC pilot | 128 × 8 | 1 mm | ≈ 25 MHz | 0.42 | 1.42 | 5,000 | ROADMAP 2028 |
| Industrial | 10⁸ / die | 5 μm | ≈ 400 MHz | 0.42 | 1.42 | 10⁶+ /yr | ROADMAP 2029+ |
Path A · MEMS pilot
6-inch wafers, 1 μm feature size, MBE for Bi₂Te₃ legs. Cycle 6-8 weeks. €25 k/wafer. Suitable for the 10-ring hex tile and small-batch delivery.
DESIGN · Q2 2027Path B · Tier-1 3D-IC
22 nm CMOS + Bi₂Te₃ back-end + 8-layer stacking. Cycle 14-18 weeks. €90 k/wafer. Yield-limited by TSV planarity, currently ≈ 40 %.
ROADMAP · 2028Materials · sourcing
Primary Bi₂Te₃ from Kurt J. Lesker or Sigma-Aldrich; permalloy from Magnetics. Half-Heusler ZrNiSn Te-free hedge for the outer ring. Recycled Te from EOL CdTe modules.
SOURCES PROVEN| Discipline | Contribution | Layer |
|---|---|---|
| Solid-state physics | Onsager coefficients, Peltier/Seebeck/Thomson | 03 |
| Topology | S¹×S¹ (torus) via stacked planar rings | 04 |
| Materials science | Bi₂Te₃ epitaxy on Si (111) with Bi₂Se₃ buffer | 03 |
| Semiconductor fab | 22 nm CMOS + back-end Bi₂Te₃ integration | 03-04 |
| Electrical engineering | 128-ch PWM driver plane, current-sense H-bridges | 04 |
| Signal processing | DFT of T(θ) → complex spectrum | 05 |
| Compiler design | PMX IR → ring schedule lowering (NWO-ASM) | 07 |
| Cryptography | Ed25519 on-die + Base 8453 anchor | 05 |
| Distributed systems | Substrate contract + free-energy routing | 08 |
| Economics | MetaStateSplitter · 35/35/30 + 15% affiliate | 09 |
Entropy production per drive cycle
Power in vs power out
Coefficient of performance envelope
Load-vs-in/out efficiency
| Mode m | Meaning | Amplitude (typ.) | Role |
|---|---|---|---|
| 0 | Uniform DC offset | < 20 mK | Global bath drift — filtered out |
| 1 | Single traveling wave | 0.5 – 2.5 K | Primary state carrier · clock |
| 2 | Standing double lobe | 0.1 – 0.6 K | Even-parity data lane |
| 3 | Triple lobe | 0.05 – 0.3 K | Odd-parity data lane |
| 4…7 | Higher harmonics | 0.01 – 0.1 K | Encrypted / paranoid modes |
Wall-outlet passthrough with embedded 24-segment STOC ring. Couples to fridge's existing ΔT via flexible copper heat pipes. No refrigerant handling, no compressor modification, any UL/CE-listed fridge is a target.
· SiFive E31 · Wi-Fi/Zigbee
· Anomaly.score kernels
· Smart-home routing
· Predictive maintenance
· Ships Q3 2027 Kickstarter
Native 22 nm RV64GC SoC with L2 SRAM cache replaced by Peltier ring array. Fridge's cold interior acts as ideal cold-side sink. Compressor duty cycle phase-locked to ring drive at ω_lock = 2·ω_compressor / N.
· Config D persistent memory
· Inventory tracking (IR + load-cell)
· Cold-chain anomaly scoring
· Customer kiosk inference
· Grocery pilot Q4 2027
Wafer-scale 8-layer 3D-IC Peltier stack. Config-E ring interconnect for rack-scale coherence. For cryogenic applications (LNG, H₂), Config-F fully thermal RISC-V core operating at μW power in the deep-cold environment.
· Config F fully thermal (cryo)
· Autonomous cold-chain logistics
· Zero-power secure data vault
· LNG / H₂ / air-separation
· Roll-out 2028-2029+
| Variant / Product | BOM € | MSRP € | GM % | Vol 2027 | Vol 2030 |
|---|---|---|---|---|---|
| I · Cryo-Plug (household retrofit) | 72 | 199 | 64 | 5,000 | 1.2 M |
| II · Commercial fridge (native) | 95 | 699 | 86 | 500 | 55 k |
| II · Commercial display case | 140 | 1,299 | 89 | 300 | 28 k |
| III · Industrial reefer | 480 | 3,499 | 86 | 50 | 4 k |
| III · LNG cryogenic node | 1,200 | 12,500 | 90 | — | 150 |
| HVAC retrofit board | 65 | 549 | 88 | — | 24 k |
| Data-centre STOC card | 320 | 2,499 | 87 | — | 5 k |
| EV BMS add-on | 28 | 199 | 86 | — | 320 k |
Fabrication
Variant I is fully commodity: SiFive/Andes MCUs, Marlow Peltier modules, Toshiba H-bridges. No cutting-edge dependencies. Variants II/III inherit Paper II supply chain: TSMC/Samsung for advanced-node CMOS, SMIC/HH-Grace as sovereign hedges.
MITIGATEDTellurium (Bi₂Te₃)
60% of refined Te is Chinese. Three hedges: (a) half-Heusler ZrNiSn Te-free substitute at 30% ZT penalty for Configs C/E/F; (b) recycled Te from EOL CdTe photovoltaics at 30% below spot; (c) NWO-ASM free-energy optimiser reroutes to CPU/GPU/QPU if STOC becomes materially constrained.
HEDGEDAppliance-OEM channel
Variant II depends on Whirlpool / Bosch / Haier / Samsung / LG / Electrolux distribution. 24-36 month product cycles, conservative silicon bets. Mitigation: license the reference design at low up-front cost; seed Variant I retrofit market first so ecosystem exists before OEMs commit.
CHANNEL RISKSubstrate contract
Every NWO-ASM substrate implements lift · dispatch · read · verify. STOC's implementation compiles PMX → ring drive schedule, dispatches via USB-C or PCIe, reads via IR-array DFT, and signs with the on-die Ed25519 key.
Portability
The stoc instruction set does not reference ring topology at the ISA level — it's a general thermodynamic-computing substrate. Other thermal-oscillation chips (linear arrays, spiral, spin-torque nano-oscillators) can implement the same contract and be routed identically.
DESIGN; ── STOC v0.1 INSTRUCTION SET ───────────────────────────── stoc.init ring N=128 R=5mm layers=8 stoc.load pmx.reg process_matrix stoc.set.mode m=1 ; azimuthal wave number stoc.set.freq omega=2.5e3 ; rad/s stoc.dir cw | ccw ; Nernst gate stoc.heat.push segment=k amount=q ; single-junction pulse stoc.heat.pull segment=k amount=q ; symmetric cool pulse stoc.oscillate cycles=n ; run n periods stoc.read.T theta -> T_out.reg ; T(theta) via IR plane stoc.read.dft N_harm -> spec.reg ; Fourier amplitudes stoc.settle tau ; wait for equilibrium stoc.dispatch poi.sig -> receipt ; sign and settle
anomaly.score(v). On STOC it compiles to:; anomaly.score(v) on the ring — canonical NWO-ASM path use stoc as target let W = pmx.lift( v ) ; encode as process matrix stoc.init ring N=128 R=5mm layers=8 stoc.load pmx.reg W stoc.set.mode m=1 stoc.set.freq omega=2.5e3 stoc.dir cw stoc.oscillate cycles=32 stoc.read.dft 8 -> spec let score = free_energy_bound( spec ) stoc.dispatch poi -> anchor(base) ; USDC settlement, splitter return (score, poi.sig)
STOC_ENDPOINT is set in the environment. The tabletop prototype will expose the endpoint over a local USB-C bridge; the wafer-scale device via PCIe Gen4.[substrate.stoc] status = "DESIGN" # flips to LIVE after Q4 2026 endpoint = "http://stoc.local:7412/v1" authentication = "bearer" # api_key from MetaState registration settlement = "base:8453" # same splitter as ASI & Metaverse affiliate = true # 15% via same splitter capabilities = [ "stoc.init", "stoc.load", "stoc.set.mode", "stoc.set.freq", "stoc.dir", "stoc.heat.push", "stoc.heat.pull", "stoc.oscillate", "stoc.read.T", "stoc.read.dft", "stoc.settle", "stoc.dispatch" ]
| Item | Part | Qty | € ea | € line |
|---|---|---|---|---|
| Peltier module | Marlow RC12-8 · 8×8 mm | 24 | 38 | 912 |
| Permalloy toroid | Magnetics 78928 · Ni-Fe 80/20 | 1 | 68 | 68 |
| FPGA dev board | Digilent Cmod A7-35T · Artix-7 | 1 | 115 | 115 |
| H-bridge driver | Toshiba TB6612 × 12 | 12 | 3 | 36 |
| IR sensor array | Melexis MLX90621 × 2 · 16-ch | 2 | 58 | 116 |
| 12 V PSU · gated | Mean Well GST60A12 · 60 W | 1 | 42 | 42 |
| USB-C bridge | FTDI FT2232HL | 1 | 22 | 22 |
| Aluminium heatsink | Custom · radial fins | 1 | 45 | 45 |
| Thermal grease + misc | Arctic MX-6 + fasteners | 1 | 35 | 35 |
| Enclosure | 3D-printed PC-FR | 1 | 60 | 60 |
| TOTAL | € 1,451 | |||
Month 1 · Procurement
BOM ordered · mechanical CAD · 3D-printed enclosure iteration · Verilog PWM engine written & simulated in Icarus.
Month 2 · Assembly
Ring assembly + thermal grease cure · heatsink brazing · power-electronics bring-up on the bench with resistive dummy loads.
Month 3 · First light
Single-segment characterisation · thermal impulse response · IR array calibration against Pt100 reference at three temperatures.
Month 4 · Full-ring drive
m = 0 (uniform) and m = 1 (traveling) modes captured · ω-sweep to extract the dispersion relation ω(m) empirically.
Month 5 · NWO-ASM binding
Register endpoint on metastate-quantum as a fifth backend · publish v0.1 of the STOC ISA · CI/CD via GitHub Actions.
Month 6 · Public demo
Run anomaly.score kernel through the ring · settle payment on Base 8453 live · release CAD/Verilog/Rust under MIT on the HF Space.
| Stage | Year | €/unit | Volume/yr | Yield | Status |
|---|---|---|---|---|---|
| Tabletop prototype | 2026 | 1,450 | 1-5 | manual · 100% | PLANNED |
| Hex tile · 10 rings | 2027 | 220 | 50-100 | ≈ 60% first pass | DESIGN |
| Wafer demo | 2027 | 90 | 200 | ≈ 40% | DESIGN |
| 3D-IC pilot | 2028 | 40 | 5,000 | ≈ 60% | ROADMAP |
| Industrial fab-out | 2029+ | 12 | 10⁶+ | ≈ 80% | ROADMAP |
github.com/RedCiprianPater/stoc-prototype under MIT.1 · Toroid preparation
Wind copper spacers around the permalloy core to define the 24 segment slots. Anneal at 850 °C in N₂ for 2 h to relieve stress. Verify μ_r ≥ 8×10³ using a Fluxgate meter before mounting Peltier modules.
STANDARD2 · Peltier mount
Apply Arctic MX-6 in a 60 μm layer (measured with a wet-film gauge). Torque each module to 0.4 N·m using an Allen key with a torque limiter. Verify with an IR camera that no segment exceeds 5 K above room ambient at rest.
STANDARD3 · Interconnect wiring
24 twisted pairs (26 AWG PTFE-insulated) from the H-bridge board to the ring. Route through a shielded loom to keep loop area < 4 cm² for EMC compliance. Terminate with polarised Molex Micro-Fit 3.0.
STANDARD4 · IR array alignment
Mount the two MLX90621 boards at 12° above and below the ring plane so their fields of view together cover the full circumference with 20 % overlap. Calibrate against a Pt100 reference at 20/40/60 °C in a small oven.
DESIGN5 · FPGA bring-up
Flash the Cmod A7-35T over USB. Verify all 24 PWM channels output 20 kHz square waves at 50 % duty into a scope. Check phase relationships — adjacent channels 15° apart, complete ring covers 360°.
DESIGN6 · First characterisation
Sweep I₀ from 0 to 1.2 A in 0.05 A steps at ω = 2.5 krad/s. Record IR array frames. Fit T(θ,t) to A·cos(mθ − ωt); extract η_ring from the residual. Target η_ring ≥ 0.10 to declare Month 3 success.
DESIGN// stoc_pwm.v — 24-channel phase-shifted PWM engine · MIT · v0.1 module stoc_pwm #( parameter N = 24, parameter PERIOD = 5000 // 20 kHz @ 100 MHz clk )( input clk, input rst, input [15:0] i0_amp, // drive amplitude input [15:0] omega, // scaled angular freq input [3:0] m_mode, // azimuthal mode output [N-1:0] pwm_out ); reg [31:0] phase [0:N-1]; reg [15:0] duty [0:N-1]; reg [15:0] counter; integer i; always @(posedge clk) begin if (rst) begin counter <= 0; for (i=0; i<N; i=i+1) phase[i] <= i * (32'h1_0000_0000 / N); end else begin counter <= (counter == PERIOD-1) ? 0 : counter + 1; for (i=0; i<N; i=i+1) begin phase[i] <= phase[i] + (omega * m_mode); duty[i] <= cos_lut(phase[i][31:22]) * i0_amp >> 12; end end end genvar g; generate for (g=0; g<N; g=g+1) assign pwm_out[g] = (counter < duty[g]) ? 1'b1 : 1'b0; endgenerate endmodule
// stoc_host.rs — MIT · v0.1 · axum + tokio + serialport use axum::{Router, routing::post, Json}; use serde::{Deserialize, Serialize}; #[derive(Deserialize)] struct DispatchReq { process_matrix: Vec<Vec<f32>>, mode: u32, // m ∈ {0,1,2,…} omega: f32, // rad/s dir: "cw" | "ccw", cycles: u32, } #[derive(Serialize)] struct DispatchResp { harmonics: Vec<(f32, f32)>, // (Re, Im) per harmonic receipt: String, // Ed25519 signature backend: String, // "stoc:tabletop-v1" } #[tokio::main] async fn main() { let app = Router::new() .route("/v1/dispatch", post(dispatch)) .route("/v1/read", post(read_dft)) .route("/v1/verify", post(verify)); axum::Server::bind(&"0.0.0.0:7412".parse().unwrap()) .serve(app.into_make_service()).await.unwrap(); }
| Metric | Target | Method | Status |
|---|---|---|---|
| η_ring @ m=1 | ≥ 0.10 | DFT fit of T(θ,t) residual | DESIGN |
| COP @ ΔT = 30 K | ≥ 4.5 | Q_C from Pt100 · W_in from current-sense | DESIGN |
| ω-dispersion linearity | R² ≥ 0.95 | ω sweep 0.5 – 5 krad/s | DESIGN |
| End-to-end kernel latency | < 200 ms | anomaly.score · N=8 · via HTTP | DESIGN |
| On-chain settlement | < 3 s post-dispatch | Base 8453 · one confirmation | PROVEN |
Read the paper (PDF)
Solid-State Thermal Oscillation Control · v1.0-DESIGN · 11 pages, two-column academic format · 14 sections + 3 appendices · all equations + honest-status table.
ResearchGate
Full preprint with author information, DOI, citation export. Pater 2026. Deposited on the ResearchGate mainline archive.
Open on ResearchGate ↗Podcast
A companion audio walking through the same material as a conversation. Same theory, physics-first framing, informal delivery.
| § | Section | Pages |
|---|---|---|
| 1 | Introduction · motivation · Second-Law reality check | 1 |
| 2 | Thermoelectric transport in a ring | 1 |
| 3 | The toroidal Peltier ring · modes · ZT* | 1 |
| 4 | Chip architecture · 9-layer 3D-IC stack | 1 |
| 5 | NWO-ASM integration · stoc substrate | 1 |
| 6 | Tabletop prototype specification · BOM | 1 |
| 7 | Scaling: prototype → industrial | 1 |
| § | Section | Pages |
|---|---|---|
| 8 | Computational model · thermal states | 1 |
| 9 | Economics · TAM · SAM · SOM | 1 |
| 10 | Geopolitics · tellurium supply chain | 1 |
| 11 | Financing · MetaStateSplitter integration | 1 |
| 12 | Honest status of every claim | 1 |
| 13 | Conclusion | 1 |
| App A/B/C | TOML stanza · ISA transcript · Risk register | 3 |
Read the paper (PDF)
RISC-V + STOC: NWO-ASM Configurations for Thermodynamic-Augmented Open-ISA Computing · v1.0-DESIGN · 10 pages, two-column academic format · 18 sections + 3 appendices · seven configuration flowcharts + honest-status table.
ResearchGate
Full preprint of Paper II with author information, DOI, citation export. Pater 2026. Deposited on the ResearchGate mainline archive.
Open on ResearchGate ↗Podcast
Companion audio walking through the seven configurations in a conversational format. Same theory, developer-first framing, informal delivery.
| § | Section | Pages |
|---|---|---|
| 1 | Introduction · why RISC-V + STOC | 1 |
| 2 | Background · RISC-V + STOC recap | 1 |
| 3 | The seven configurations · matrix + summary | 1 |
| 4 | Config A · RV core + STOC coprocessor | 1 |
| 5 | Config B · Peltier thermal L2 cache | 1 |
| 6 | Config C · STOC integer ALU | 1 |
| 7 | Config D · STOC persistent memory | 1 |
| 8 | Config E · STOC ring interconnect | 1 |
| 9 | Config F · Fully thermal RISC-V | 1 |
| § | Section | Pages |
|---|---|---|
| 10 | Config G · Distributed RV+STOC swarm | 1 |
| 11 | NWO-ASM · precise build requirements per config | 1 |
| 12 | Development plan · nine-quarter roadmap | 1 |
| 13 | Economics · per-die cost + market segmentation | 1 |
| 14 | Supply-chain risk · RISC-V fab + Te dominance | 1 |
| 15 | Adoption prospects · 3-phase path | 1 |
| 16 | Honest status of every claim | 1 |
| 17 | Conclusion · references | 1 |
| App A/B/C | Boot sequence · opcode encoding · risk register | 3 |
Read the paper (PDF)
STOC-Cooled Compute: Refrigeration Systems and Industrial Cooling Infrastructure as Distributed Thermodynamic Computing Nodes · v1.0-DESIGN · 11 pages, two-column academic format · 15 sections + 4 wide appendices · 5 figures.
ResearchGate
Full preprint of Paper III with author information, DOI, citation export. Pater 2026. Deposited on the ResearchGate mainline archive as publication 412123752.
Open on ResearchGate ↗Podcast · COLDCOMPUTE
Companion audio walking through the STOC-Cooling framework: the three variants, ten verticals, economics, and the path to global thermal compute.
| § | Section | Pages |
|---|---|---|
| 1 | Introduction · the world runs on ΔT | 1 |
| 2 | Background · STOC + substrate contract | 1 |
| 3 | Entropy in a bounded cooling system | 1 |
| 4 | Three canonical variants (I / II / III) | 1 |
| 5 | Ten cooling verticals · deep dive | 2 |
| 6 | Thermal-electrical coupling model | 1 |
| 7 | NWO-ASM integration per variant | 1 |
| 8 | Development plan · 6-stage roadmap | 1 |
| § | Section | Pages |
|---|---|---|
| 9 | Economics · BOM & margin | 1 |
| 10 | Market analysis · TAM/SAM/SOM | 1 |
| 11 | Supply-chain risk | 1 |
| 12 | Adoption prospects · 3-phase | 1 |
| 13 | Honest status of every claim | 1 |
| 14 | Conclusion · references | 1 |
| App A | 14-vertical integration matrix | 1 |
| App B/C/D | Cryo-Plug BOM · Industrial BOM · Risk register | 3 |
Revenue vs cost · 4-year projection
Unit cost trajectory · €/die
Cumulative units shipped
Revenue mix by stream
| Share | Wallet | Role |
|---|---|---|
| Guardian · 35% | 0x2E964e1c0e3Fa2C0dfD484B2E6D2189dfCF20958 | Audit + oversight |
| Savings · 35% | 0x86adACe73556FD7b386B5E469eEC0878073d6D30 | R&D reserve |
| Operations · 30% | 0x4f125e835bbc9BbB77607C66dE6D0d32339B936c | Manufacturing runway |
| Affiliate · +15% | referrer address (set at registration) | Atomic same-tx payout |
| Line item · € 000s | 2026 | 2027 | 2028 | 2029 | 2030 |
|---|---|---|---|---|---|
| Hardware revenue | 18 | 320 | 2,100 | 10,400 | 36,200 |
| NWO-ASM licensing | 0 | 15 | 140 | 820 | 3,800 |
| Vertical consumption (ASI+Metaverse) | 0 | 25 | 180 | 950 | 2,400 |
| Total revenue | 18 | 360 | 2,420 | 12,170 | 42,400 |
| COGS · materials + fab | 4 | 85 | 720 | 3,600 | 15,300 |
| R&D · engineering | 320 | 1,120 | 2,400 | 3,600 | 4,800 |
| G&A · overhead | 75 | 380 | 1,050 | 1,600 | 2,100 |
| EBITDA | −381 | −1,225 | −1,750 | 3,370 | 20,200 |
| Cumulative EBITDA | −381 | −1,606 | −3,356 | 14 | 20,214 |
| Method | Assumption | Result (2030) |
|---|---|---|
| DCF · explicit 5-yr | WACC 22 % · g 3 % · terminal 10× EBITDA | € 68 M |
| Revenue multiple · comp | Median deep-tech chip × 1.6 | € 68 M |
| Peer transaction · comp | Seed-stage sensor-chip median | € 55–90 M |
| Midpoint estimate | ≈ € 70 M equity value at 2030 industrial ramp | |
| Round | Amount raised | Purpose | Timing |
|---|---|---|---|
| Pre-seed · shared | € 0 – 500 k | Tabletop prototype + first-light characterisation | 2026 · NOW |
| Seed · shared | € 500 k – 2 M | MEMS pilot line + hex-tile production | 2027 H2 |
| Series A · shared | € 2 – 8 M | Tier-1 3D-IC engagement + pilot line | 2028 H1 |
| Growth · shared | € 8 – 25 M | Industrial fab-out · yield ramp | 2029+ |
Total raised (all three products)
Capital raised over time
Recent activity
| Block | Time | From | Amount (ETH) | Tx |
|---|---|---|---|---|
| Loading recent deposits… | ||||
| What | Value |
|---|---|
| Network | Base Mainnet · chain id 8453 |
| Splitter (shared) | 0x33c22FE36557Ad13C838A2Eb465510CF173046bc |
| Settlement token | USDC · 0x8335…2913 |
| Deposit function | deposit() payable · or approve+payForInference() |
| Split | 35% guardian · 35% savings · 30% ops · +15% affiliate (same tx) |
| Immutability | Verified & unowned · no upgrade key |